This invention relates to memory barrier instructions for enforcing a desired order of execution for memory instructions in a multi-socket, multi-core computing system.
In general, a computer program written by a computer programmer includes a number of operations for accessing memory in the computer system. In the computer program, the memory operations have an order specified by the computer programmer. In many modern computing systems, the memory is shared among multiple devices such as multiple processing elements and memory-mapped peripherals (e.g., I/O devices).
Due to the memory being shared among multiple devices in the computing system, the memory operations may potentially be executed in an order other than the order specified by the user. In some examples, such “out of order” memory operations have no side effects. In other examples, out of order memory operations can adversely affect the behavior of the computer program. For example, reordering of a first instruction that writes a memory address and a second instruction that reads the memory address to obtain the result of the first instruction may result in an incorrect value being read by the second instruction.
To manage out of order memory operations, many modern processor architectures implement memory barrier instructions. Very generally, memory barrier instructions enforce an ordering constraint on memory operations issued before and after the memory barrier instruction. In some examples, memory operations issued before a memory barrier instruction are guaranteed to have completed before memory operations issued after the memory barrier instruction.